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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers 19-5040; rev 0; 10/09 note: this device is specified over the -40 n c to +85 n c extended temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ordering information/selector guide general description the MAX16068 flash-configurable system manager monitors and manages up to six system voltages simultaneously. the MAX16068 integrates an analog- to-digital converter (adc). device configuration infor - mation, including overvoltage and undervoltage limits, time delay settings is stored in nonvolatile flash memory. during a fault condition, fault flags and channel volt - ages can be automatically stored in the nonvolatile flash memory for later readback. the internal 1% accurate, 10-bit adc measures each input and compares the result to one overvoltage and one undervoltage limit. a fault signal asserts when a monitored voltage falls outside the set limits. the MAX16068 supports a power-supply voltage of up to 14v and can be powered directly from the 12v interme - diate bus in many systems. the MAX16068 includes six programmable general- purpose inputs/outputs (gpios). gpios are flash con - figurable as a fault output, as a watchdog input or output, or as a manual reset. the MAX16068 features nonvolatile fault memory for recording information during system shutdown events. the fault logger records a failure in the internal flash and sets a lock bit protecting the stored fault data from accidental erasure. an smbus? or a jtag serial interface configures the MAX16068. the MAX16068 is available in a 28-pin, 5mm x 5mm, tqfn package and is fully specified over the -40 n c to +85 n c extended temperature range. features s operates from 2.8v to 14v s 1% accurate, 10-bit adc monitors 6 voltage inputs s analog en monitoring input s 6 monitored inputs with overvoltage and undervoltage limits s nonvolatile fault event logger s six general-purpose inputs/outputs configurable as: dedicated fault output watchdog timer function manual reset smbus alert fault propagation input/output s smbus and jtag interface s supports cascading with max16065/max16066 s flash-configurable time delays and thresholds s -40 n c to +85 n c extended operating temperature range applications networking equipment telecom equipment (base stations, access) storage/raid systems servers typical operating circuit appears at end of data sheet. smbus is a trademark of intel corp. part pin-package voltage-detector inputs general-purpose inputs/ outputs MAX16068eti+ 28 tqfn-ep* 6 6
2 ______________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ............... .-0.3v to +15v mon_, scl, sda, a0 to gnd ................................ -0.3v to +6v en, tck, tms, tdi to gnd .................................... -0.3v to +4v tdo to gnd ............................................ -0.3v to (v dbp + 0.3v) reset, gpio_ (configured as open-drain) to gnd. .................... -0.3v to +6v reset, gpio_ (configured as push-pull) to gnd ................................................. -0.3v to (v dbp + 0.3v) dbp, abp to gnd ....................................... -0.3v to minimum of (4v and (v cc + 0.3v)) continuous current (all pins) .......................................... q 20ma continuous power dissipation (t a = +70 n c) 28-pin tqfn (derate 34.5mw/ n c above +70 n c) ..... 2759mw* thermal resistance (note 1) b ja ................................................................................ 29 n c/w b jc ........................ . 2 n c/w operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c electrical characteristics ( v cc = 2.8v to 14v, t a = t j = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 2) absolute maximum ratings *as per jedec 51 standard, multilayer board (pcb). note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units operating voltage range v cc reset output asserted low 1.2 v 2.8 14 undervoltage lockout v uvlo minimum voltage on v cc to ensure the device is flash configurable 2.7 v undervoltage lockout hysteresis uvlo hys 55 mv minimum flash operating voltage v flash minimum voltage on v cc to ensure flash erase and write operations 2.7 v supply current i cc1 no load on any output 2.8 4 ma i cc2 no load on any output, during flash writing cycle 7.7 14 v cc = v abp = v dbp = 3.6v (note 3) 5 dbp regulator voltage v dbp v cc = 5v, c dbp = 1 f f, no load 2.8 3 3.2 v abp regulator voltage v abp v cc = 5v, c abp = 1 f f, no load 2.85 3 3.15 v boot time t boot v cc > v uvlo 100 200 f s flash writing time 8-byte word 122 ms internal timing accuracy (note 4) -10 +10 % adc resolution 10 bits gain error adc gain t a = +25 n c 0.35 % t a = -40 n c to +85 n c 0.75 offset error adc off 1.5 lsb
_______________________________________________________________________________________ 3 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers electrical characteristics (continued) ( v cc = 2.8v to 14v, t a = t j = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 2) parameter symbol conditions min typ max units integral nonlinearity adc inl 1 lsb differential nonlinearity adc dnl 1 lsb adc total monitoring cycle time t cycle monitoring all 6 inputs, no mon_ fault detected 24 30 f s adc mon_ ranges adc rng mon_ range set to 00 5.552 v mon_ range set to 01 2.776 mon_ range set to 10 1.388 adc lsb step size adc lsb mon_ range set to 00 5.42 mv mon_ range set to 01 2.71 mon_ range set to 10 1.35 adc input leakage current 1 f a enable input (en) en input-voltage threshold v th_en_r en voltage rising 1.24 v v th_en_f en voltage falling 1.195 1.215 1.235 en input current i en -0.5 +0.5 f a en input-voltage range 0 3.6 v outputs (reset, gpio_) output-voltage low v ol i sink = 2ma 0.4 v i sink = 10ma, gpio_ only 0.7 v cc = 1.2v, i sink = 100 f a (reset only) 0.3 maximum output sink current total current into reset, gpio_, v cc = 3.3v 18 ma output-voltage high (push-pull) v oh i source =100 f a 2.4 v output leakage current (open-drain) i out_lkg 1 f a inputs (a0, gpio_) input logic-low v il 0.8 v input logic-high v ih 20 v wdi pulse width t wdi 100 ns mr pulse width t mr 2 f s smbus interface logic-input low voltage v il input voltage falling 0.8 v logic-input high voltage v ih input voltage rising 2.0 v input leakage current v cc shorted to gnd, v mon_ = 0 or 6v -1 +1 f a output sink current v ol i sink = 3ma 0.4 v input capacitance c in 5 pf
4 ______________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers electrical characteristics (continued) ( v cc = 2.8v to 14v, t a = t j = -40 n c to +85 n c, unless otherwise specified. typical values are at v abp = v dbp = v cc = 3.3v, t a = +25 n c.) (note 2) note 2: specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at t a = +25 n c and t a = +85 n c. specifications at t a = -40 n c are guaranteed by design. note 3: for v cc of 3.6v or lower, connect v cc , dbp, and abp together. for higher supply applications, connect only v cc to the supply rail. note 4: applies to reset (except for a reset timeout period of 25 f s), fault, autoretry, sequence delays, and watchdog timeout. parameter symbol conditions min typ max units smbus timing serial clock frequency f scl 400 khz bus free time between stop and start condition t buf 1.3 f s start condition setup time t su:sta 0.6 f s start condition hold time t hd:sta 0.6 f s stop condition setup time t su:sto 0.6 f s clock low period t low 1.3 f s clock high period t high 0.6 f s data setup time t su:dat 100 ns output fall time t of 10pf p c bus p 400pf 250 ns data hold time t hd:dat from 50% scl falling to sda change receive 0.15 f s transmit 0.3 0.9 pulse width of spike suppressed t sp 250 ns smbus timeout t timeout smbclk time low for reset 22 35 ms jtag interface tdi, tms, tck logic-low input voltage v il input voltage falling 0.8 v tdi, tms, tck logic-high input voltage v ih input voltage rising 2.0 v tdo logic-output low voltage v ol_tdo i sink = 3ma 0.4 v tdo logic-output high voltage v oh_tdo i source = 200 f a 2.4 v tdi, tms pullup resistors r jpu pullup to dbp 30 50 65 k i i/o capacitance c i/o 5 pf tck clock period t 1 1000 ns tck high/low time t 2, t 3 50 500 ns tck to tms, tdi setup time t 4 15 ns tck to tms, tdi hold time t 5 15 ns tck to tdo delay t 6 500 ns tck to tdo high-z delay t 7 500 ns
_______________________________________________________________________________________ 5 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers figure 1. smbus timing diagram figure 2. jtag timing diagram stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition tck t 1 t 2 t 3 t 4 t 5 t 6 t 7 tdi, tms tdo
6 ______________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers typical operating characteristics (typical values are at v cc = 3.3v, t a = +25 n c.) v cc supply current vs. v cc supply voltage MAX16068 toc01 v cc (v) i cc (ma) 12 10 2 4 6 8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0 14 t a = -40c t a = +25c t a = +85c abp and dbp connected to v cc abp and dbp regulators active normalized mon_threshold vs. temperature temperature (c) normalized mon_ threshold 80 60 40 20 0 -20 0.965 0.980 0.995 1.010 1.025 1.040 1.055 0.950 -40 MAX16068 toc02 5.6v range half-scale puv threshold normalized en threshold vs. temperature temperature (c) normalized en threshold 80 60 40 20 0 -20 0.965 0.980 0.995 1.010 1.025 1.040 1.055 0.950 -40 MAX16068 toc03 transient duration vs. threshold overdrive (en) en overdrive (mv) transient duration ( s) 10 5 10 15 20 25 30 35 0 1 100 MAX16068 toc04 normalized timing accuracy vs. temperature temperature (c) normalized slot delay 80 60 40 20 0 -20 0.965 0.980 0.995 1.010 1.025 1.040 1.055 0.950 -40 MAX16068 toc05 transient duration vs. mon_ deglitch deglitch value transient duration (us) 16 8 4 10 20 30 40 50 60 70 80 90 0 2 MAX16068 toc06
_______________________________________________________________________________________ 7 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers typical operating characteristics (continued) (typical values are at v cc = 3.3v, t a = +25 n c.) mr to reset propagation delay vs. temperature temperature (c) delay (ns) 80 60 40 20 0 -20 -40 MAX16068 toc07 200 300 400 500 600 700 800 900 1000 1100 100 max min output voltage vs. sink current (out = low) i sink (ma) v out (v) 15 10 5 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0 20 MAX16068 toc08 reset, gpio_ output-voltage high vs. source current (push-pull output) i source (a) v out (v) 1000 800 600 400 200 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 2.4 0 1200 MAX16068 toc09 reset gpio_ differential nonlinearity vs. code MAX16068 toc11 code (lsb) dnl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 integral nonlinearity vs. code MAX16068 toc10 code (lsb) inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 reset output current vs. v cc supply voltage v cc (v) output current (ma) 12 10 8 6 4 2 5 10 15 20 25 0 0 14 MAX16068 toc12 abp and dbp connected to v cc abp and dbp regulators active v reset = 0.3v
8 ______________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers pin description pin configuration MAX16068 thin qfn (5mm x 5mm) top view 26 27 25 24 10 9 11 12 1 2 4 5 6 7 ep* 20 21 19 17 16 15 3 18 28 8 + 23 13 22 14 gpio4 gpio6 gnd ao scl gpio3 mon1 abp v cc mon2 dbp en mon5 mon6 reset n.c. tms tck tdi gpio5 gnd gpio1 tdo gpio2 sda mon4 n.c. mon3 *connect exposed pad to gnd. pin name function 1C4, 27, 28 gpio3C gpio6, gpio1, gpio2 general-purpose inputs/outputs. each gpio_ can be configured to act as an input, a push-pull output, an open-drain output, or a special function. 5, 19 gnd ground. connect all gnds together. 6 a0 four-state smbus address. address is sampled upon por. 7 scl smbus serial-clock input 8 sda smbus serial-data open-drain input/output 9 tdo jtag test data output 10 tdi jtag test data input 11 tck jtag test clock 12 tms jtag test mode select 13, 14 n.c. no connection. not internally connected. 15 en analog enable input. all outputs deassert when v en is below the enable threshold.
_______________________________________________________________________________________ 9 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers pin description (continued) functional diagram gpio6 wdo gpio5 wdi gpio4 mr gpio3 fault gpio2 extfault gpio1 alert ao scl sda ref reg decode logic watchdog timer digital comparators gpio control reset abp v cc dbp reset output logic ram registers flash registers smbus interface jtag interface adc registers 10-bit adc (sar) en v th_en mon1 mon2 mon3 mon4 mon5 mon6 tdo tdi tck tms gnd gnd MAX16068 voltage and scaling mux pin name function 16 dbp digital bypass. all push-pull outputs are referenced to dbp. bypass dbp with a 1 f f capacitor to gnd. 17 v cc power-supply input. bypass v cc to gnd with a 10 f f ceramic capacitor. 18 abp analog bypass. bypass abp to gnd with a 1 f f ceramic capacitor. 20C25 mon1C mon6 monitor voltage inputs. set the monitor voltage range through the configuration registers. measured values are written to the adc registers and can be read back through the smbus or jtag interface. 26 reset configurable reset output ep exposed pad. internally connected to gnd. connect to ground, but do not use ep as the main ground connection.
10 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers detailed description the MAX16068 monitors up to six system power sup - plies. the monitoring phase begins after boot-up if en is high and the software enable bit is set to 1. an internal multiplexer cycles through each mon_ input. at each multiplexer stop, the 10-bit adc converts the monitored analog voltage to a digital result and stores the result in a register. each time a conversion cycle (5 f s, max) com - pletes, internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. when a result violates a programmed threshold, the conversion can be configured to generate a fault. gpio_ can be programmed to assert on combi - nations of faults. additionally, faults can be configured to trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write-protects the data to prevent accidental erasure. the MAX16068 contains both smbus and jtag serial interfaces for accessing registers and flash. use only one interface at any given time. for more information on how to access the internal memory through these interfaces, see the smbus-compatible serial interface and jtag serial interface sections. the memory map is divided into three pages with access controlled by special smbus and jtag commands. the factory-default values at por (power-on reset) for all ram registers are 0s. por occurs when v cc reaches the undervoltage-lockout threshold (uvlo) of 2.7v (max). at por, the device begins a boot-up sequence. during the boot-up sequence, all monitored inputs are masked from initiating faults and flash contents are copied to the respective register locations. during boot- up, the MAX16068 is not accessible through the serial interface. the boot-up sequence takes up to 150 f s, after which the device is ready for normal operation. reset is asserted low up to the boot-up phase after which it assumes its programmed active state. reset remains active for its programmed timeout period once all moni - tored channels are within their respective thresholds. up to the boot-up phase, the gpio_s are high impedance. power apply 2.8v to 14v to v cc to power the MAX16068. bypass v cc to ground with a 10 f f capacitor. two inter - nal voltage regulators, abp and dbp, supply power to the analog and digital circuitry within the device. for operation at 3.6v or lower, disable the regulators by con - necting abp and dbp to v cc . abp is a 3.0v (typ) voltage regulator that powers the inter - nal analog circuitry. bypass abp to gnd with a 1 f f ceram - ic capacitor installed as close as possible to the device. dbp is an internal 3.0v (typ) voltage regulator. dbp powers flash and digital circuitry. all push-pull outputs refer to dbp. dbp supplies the input voltage to the inter - nal charge pump when the programmable outputs are configured as charge-pump outputs. bypass the dbp output to gnd with a 1 f f ceramic capacitor installed as close as possible to the device. do not power external circuitry from abp or dbp. enable input (en) to enable monitoring, the voltage at en must be above 1.24v (typ) and the software enable bit in r73h[0] must be set to 1. to disable monitoring, either pull en below 1.215v (typ) or set the software enable bit to 0. see table 1 for the software enable bit configurations. connect en to abp if not used. table 1. software enable configurations register address flash address bit range description 73h 273h [0] software enable 1 = sequencing enabled 0 = power-down [1] reserved [2] 1 = margin mode enabled [3] reserved [4] independent watchdog mode enable 1 = watchdog timer is independent of en input 0 = watchdog timer boots after en goes high and the boot-up delay completes
______________________________________________________________________________________ 11 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers when in the monitoring state, and when en falls below the undervoltage threshold, a register bit, enreset (r20h[2]), is set to a 1. this register bit latches and must be cleared through software. this bit indicates if reset asserted low due to en going under the threshold. the por state of enreset is 0. the bit is only set on a fall - ing edge of the en comparator output or the software enable bit. if operating in latch-on fault mode, toggle en or toggle the software enable bit to clear the latch condition and restart the device once the fault condition has been removed. set r73h[2] to 1 to enable monitoring functionality. faults are not recorded when the device is in margining mode. set r73h[2] to 0 for normal functionality. voltage monitoring the MAX16068 features an internal 10-bit adc that mon - itors the mon_ voltage inputs. an internal multiplexer cycles through each of the enabled inputs, taking less than 24 f s for a complete monitoring cycle. each acquisi - tion takes approximately 4 f s. at each multiplexer stop, the 10-bit adc converts the analog input to a digital result and stores the result in a register. adc conversion results are stored in registers r00hCr0bh (see table 2). use the smbus or jtag serial interface to read adc conversion results. the MAX16068 provides six inputs, mon1Cmon6, for voltage monitoring. each input-voltage range is pro - grammable in registers r43hCr44h (see table 3). when mon_ configuration registers are set to 11, mon_ volt - ages are not monitored and the multiplexer does not stop at these inputs, decreasing the total cycle time. these inputs cannot be configured to trigger fault conditions. the two programmable thresholds for each monitored voltage include an overvoltage and an undervoltage threshold. see the faults section for more information on setting overvoltage and undervoltage thresholds. all voltage thresholds are 8 bits wide. the 8 msbs of the 10-bit adc conversion result are compared to these overvoltage and undervoltage thresholds. for any undervoltage or overvoltage condition to be monitored and any faults detected, the mon_ input must be assigned to monitoring mode. inputs that are not enabled are not converted by the adc; they contain the last value acquired before that channel was disabled. the adc conversion result registers are reset to 00h at boot-up. these registers are not reset when a reboot command is executed. to temporarily disable voltage monitoring during volt - age margining conditions, set r73h[2] to 1 to enable margining mode functionality. faults (except for faults triggered by extfault being pulled low externally) are not recorded when the device is in margining mode, but the adc continues to run and conversion results con - tinue to be available. set r73h[2] back to 0 for normal functionality. table 2. adc conversion results (read only) register address bit range description 00h [7:0] mon1 result (msb) 01h [7:6] mon1 result (lsb) 02h [7:0] mon2 result (msb) 03h [7:6] mon2 result (lsb) 04h [7:0] mon3 result (msb) 05h [7:6] mon3 result (lsb) 06h [7:0] mon4 result (msb) 07h [7:6] mon4 result (lsb) 08h [7:0] mon5 result (msb) 09h [7:6] mon5 result (lsb) 0ah [7:0] mon6 result (msb) 0bh [7:6] mon6 result (lsb)
12 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers boot-up delay once en is above its threshold and the software enable bit is set, a boot-up delay occurs before monitoring begins. this delay is configured in register 77h as shown in table 4, and it is stored as an 8-bit value calculated as follows: t boot = (5 x 10 -6 ) x 2 a x (16 + b) + 480s where t boot is in seconds, a is the decimal value of the 4 msbs and b is the decimal value of the 4 lsbs. table 4. boot-up delay table 3. adc configuration registers register address flash address bit range description 43h 243h [1:0] mon1 full-scale range 00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [3:2] mon2 full-scale range 00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [5:4] mon3 full-scale range 00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [7:6] mon4 full-scale range 00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted 44h 244h [1:0] mon5 full-scale range 00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [3:2] mon6 full-scale range 00 = 5.6v 01 = 2.8v 10 = 1.4v 11 = channel not converted [7:4] not used register address flash address bit range description 77h 277h [7:0] boot-up delay
______________________________________________________________________________________ 13 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers general-purpose inputs/outputs gpio1Cgpio6 are programmable general-purpose inputs/outputs. gpio1Cgpio6 are configurable as a manual reset input, a watchdog timer input and output, logic inputs/outputs, and fault-dependent outputs. when programmed as outputs, gpio_s are open-drain or push-pull. see tables 5 and 6 for more detailed informa - tion on configuring gpio1Cgpio6. when gpio1Cgpio6 are configured as general-pur - pose inputs/outputs, read values from the gpio_ ports through r1eh and write values to gpio_s through r3eh. note that r3eh has a corresponding flash register, which programs the default state of a general-purpose output. see table 7 for more information on reading and writing to the gpio_. table 5. gpio_ configuration registers table 6. gpio_ function configuration bits table 7. gpio_ state registers register address flash address bit range description 3fh 23fh [1:0] gpio1 configuration [3:2] gpio2 configuration [5:4] gpio3 configuration [7:6] gpio4 configuration 40h 240h [1:0] gpio5 configuration [3:2] gpio6 configuration [4] araen bit [7:5] not used gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 00 logic input logic input logic input logic input logic input logic input 01 logic output (push-pull) logic output (push-pull) logic output (push-pull) logic output (push-pull) logic output (push-pull) logic output (push-pull) 10 logic output (open drain) logic output (open drain) logic output (open drain) logic output (open drain) logic output (open drain) logic output (open drain) 11 alert (open drain) fault (open drain) mr input wdi wdo (open drain) extfault (open drain) register address flash address bit range description 1eh [0] gpio1 input state [1] gpio2 input state [2] gpio3 input state [3] gpio4 input state [4] gpio5 input state [5] gpio6 input state [7:6] not used 3eh 23eh [0] gpio1 output state [1] gpio2 output state [2] gpio3 output state [3] gpio4 output state [4] gpio5 output state [5] gpio6 output state [7:6] not used
14 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers alert gpio1 is configurable as the smbus alert signal, alert . alert asserts when any fault condition occurs. when the smbus host sends the ara (alert response address), the MAX16068 responds with its slave address and deasserts alert . alert is an open-drain output. set the araen bit in r40h[4] to 1 to disable the ara feature. under these conditions, the device does not respond to an ara on the smbus line. fault gpio2 is configurable as a dedicated fault output, fault. fault asserts when an overvoltage or under - voltage condition occurs on the selected inputs. fault dependencies are set using registers r36h and r37h (see table 8). when fault depends on more than one mon_, the fault output asserts when one or more mon_ exceeds a programmed threshold voltage. fault acts independently of the critical fault system, described in the critical faults section. use r37h[7] to set the polarity of fault. manual reset ( mr ) gpio3 is configurable to act as an active-low manual reset input, mr . drive mr low to assert reset. reset remains asserted for the selected reset timeout period after mr transitions from low to high. when connecting mr to a push - button, use a pullup resistor. see the reset output section for more information on selecting a reset timeout period. watchdog input (wdi) and output ( wdo ) gpio4 and gpio5 are configurable as the watchdog timer input (wdi) and output, wdo , respectively. see table 16 for configuration details. wdo is an open-drain, active-low output. see the watchdog timer section for more information about the operation of the watchdog timer. external fault ( extfault ) gpio6 is configurable as the external fault input/output, extfault . extfault asserts if any monitored volt - age exceeds an overvoltage or undervoltage threshold. extfault also asserts if a power-up or power-down sequencing fault occurs. this signal can be used to cascade multiple MAX16068s. for the MAX16068, if register bit r6dh[2] is set in addi - tion to r72h[5], extfault going low triggers a nonvola - tile fault log operation. table 8. fault dependencies register address flash address bit range description 36h 236h [0] fault depends on mon1 undervoltage threshold [1] fault depends on mon2 undervoltage threshold [2] fault depends on mon3 undervoltage threshold [3] fault depends on mon4 undervoltage threshold [4] fault depends on mon5 undervoltage threshold [5] fault depends on mon6 undervoltage threshold [7:6] not used 37h 237h [0] fault depends on mon1 overvoltage threshold [1] fault depends on mon2 overvoltage threshold [2] fault depends on mon3 overvoltage threshold [3] fault depends on mon4 overvoltage threshold [4] fault depends on mon5 overvoltage threshold [5] fault depends on mon6 overvoltage threshold [6] not used [7] 0 = fault is an active-low digital output 1 = fault is an active-high digital output
______________________________________________________________________________________ 15 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers faults the MAX16068 monitors the input (mon_) channels and compares the results with an overvoltage threshold and an undervoltage threshold. based on these conditions, the MAX16068 asserts various fault outputs and save specific information about the channel conditions and voltages into the nonvolatile flash. once a critical fault event occurs, the failing channel condition, adc conver - sions at the time of the fault, or both can be saved by configuring the event logger. the event logger records a single failure in the internal flash and sets a lock bit that protects the stored fault data from accidental erasure on a subsequent power-up. the MAX16068 is capable of measuring overvoltage and undervoltage fault events. fault conditions are detected at the end of each adc conversion. an over - voltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. an undervoltage event occurs when the voltage at a monitored input falls below the undervoltage threshold. fault thresholds are set in registers r49hCr59h as shown in table 9. disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. only the upper 8 bits of a conversion result are com - pared with the programmed fault thresholds. table 9. fault threshold registers register address flash address bit range description 48h 248h [7:0] not used 49h 249h [7:0] mon1 overvoltage threshold 4ah 24ah [7:0] mon1 undervoltage threshold 4bh 24bh [7:0] not used 4ch 24ch [7:0] mon2 overvoltage threshold 4dh 24dh [7:0] mon2 undervoltage threshold 4eh 24eh [7:0] not used 4fh 24fh [7:0] mon3 overvoltage threshold 50h 250h [7:0] mon3 undervoltage threshold 51h 251h [7:0] not used 52h 252h [7:0] mon4 overvoltage threshold 53h 253h [7:0] mon4 undervoltage threshold 54h 254h [7:0] not used 55h 255h [7:0] mon5 overvoltage threshold 56h 256h [7:0] mon5 undervoltage threshold 57h 257h [7:0] not used 58h 258h [7:0] mon6 overvoltage threshold 59h 259h [7:0] mon6 undervoltage threshold
16 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers deglitch fault conditions are detected at the end of each conver - sion. when the voltage on an input falls outside a moni - tored threshold for one acquisition, the input multiplexer remains on that channel and performs several succes - sive conversions. to trigger a fault, the input must stay outside the threshold for a certain number of acquisitions as determined by the deglitch setting in r74h[6:5] (see table 10). fault flags fault flags indicate the fault status of a particular input. the fault flag of any monitored input in the device can be read at any time from registers r1bh and r1ch, as shown in table 11. clear a fault flag by writing a 1 to the appro - priate bit in the flag register. unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see table 12). the fault flag is only set when the matching enable bit in the critical fault enable register is also set. table 10. deglitch configuration table 11. fault flags register address flash address bit range description 74h 274h [6:5] voltage comparator deglitch configuration 00 = 2 cycles 01 = 4 cycles 10 = 8 cycles 11 = 16 cycles register address bit range description 1bh [0] mon1 undervoltage threshold [1] mon2 undervoltage threshold [2] mon3 undervoltage threshold [3] mon4 undervoltage threshold [4] mon5 undervoltage threshold [5] mon6 undervoltage threshold [7:6] reserved 1ch [0] mon1 overvoltage threshold [1] mon2 overvoltage threshold [2] mon3 overvoltage threshold [3] mon4 overvoltage threshold [4] mon5 overvoltage threshold [5] mon6 overvoltage threshold [6] external fault ( extfault ) [7] smb alert
______________________________________________________________________________________ 17 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers if gpio6 is configured as the extfault input/output and extfault is pulled low by an external circuit, bit r1ch[6] is set. the smb alert ( alert ) bit is set if the MAX16068 has asserted the smbus alert output. clear by writing a 1. see the smbalert ( alert ) section for more details. critical faults during normal operation, a fault condition can be stored in the flash memory by setting the appropriate critical fault enable bits. set the appropriate critical fault enable bits in registers r6ehCr72h (see table 12) for a fault con - dition to trigger a critical fault. table 12. critical fault configuration register address flash address bit range description 6dh 26dh [1:0] fault information to log 00 = save failed line flags and adc values in flash 01 = save only failed line flags in flash 10 = save only adc values in flash 11 = do not save anything [2] 1 = fault log triggered when extfault is pulled low externally [7:3] not used 6eh 26eh [0] 1 = fault log triggered when mon1 is below its undervoltage threshold [1] 1 = fault log triggered when mon2 is below its undervoltage threshold [2] 1 = fault log triggered when mon3 is below its undervoltage threshold [3] 1 = fault log triggered when mon4 is below its undervoltage threshold [4] 1 = fault log triggered when mon5 is below its undervoltage threshold [5] 1 = fault log triggered when mon6 is below its undervoltage threshold [7:6] not used 6fh 26fh [3:0] not used [4] 1 = fault log triggered when mon1 is above its overvoltage threshold [5] 1 = fault log triggered when mon2 is above its overvoltage threshold [6] 1 = fault log triggered when mon3 is above its overvoltage threshold [7] 1 = fault log triggered when mon4 is above its overvoltage threshold 70h 270h [0] 1 = fault log triggered when mon5 is above its overvoltage threshold [1] 1 = fault log triggered when mon6 is above its overvoltage threshold [7:2] not used 71h 271h [7:0] not used 72h 272h [4:0] not used [5] 1 = extfault pulled low externally causes the device to stop monitoring until en is toggled or the autoretry delay expires (see autoretry/latch mode section) 0 = extfault pulled low externally does not cause the device to stop monitoring [7:6] not used
18 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers logged fault information is stored in flash registers r200hCr208h (see table 13). after fault information is logged, the flash is locked and must be unlocked to enable a new fault log to be stored. write a 0 to r8ch[1] to unlock the configuration flash. fault information can be configured to store adc conversion results and/or fault flags in registers. select the critical fault configura - tion in r6dh[1:0]. set r6dh[1:0] to 11 to turn off the fault logger. all stored adc results are 8 bits wide (msbs of the conversion). autoretry/latch mode the MAX16068 can be configured for one of two fault management methods: autoretry or latch-on-fault. set r74h[4:3] to 00 to select the latch-on-fault mode. the device does not reinitiate monitoring until en is toggled or the software enable bit is toggled. see the enable input (en) section for more information on setting the software enable bit. table 13. nonvolatile fault log registers flash address bit range description 200h [7:0] reserved 201h [0] fault log triggered on mon1 falling below its undervoltage threshold [1] fault log triggered on mon2 falling below its undervoltage threshold [2] fault log triggered on mon3 falling below its undervoltage threshold [3] fault log triggered on mon4 falling below its undervoltage threshold [4] fault log triggered on mon5 falling below its undervoltage threshold [5] fault log triggered on mon6 falling below its undervoltage threshold [7:6] not used 202h [0] fault log triggered on mon1 exceeding its overvoltage threshold [1] fault log triggered on mon2 exceeding its overvoltage threshold [2] fault log triggered on mon3 exceeding its overvoltage threshold [3] fault log triggered on mon4 exceeding its overvoltage threshold [4] fault log triggered on mon5 exceeding its overvoltage threshold [5] fault log triggered on mon6 exceeding its overvoltage threshold [6] fault log triggered on extfault [7] not used 203h [7:0] mon1 adc output (8 msbs) 204h [7:0] mon2 adc output (8 msbs) 205h [7:0] mon3 adc output (8 msbs) 206h [7:0] mon4 adc output (8 msbs) 207h [7:0] mon5 adc output (8 msbs) 208h [7:0] mon6 adc output (8 msbs)
______________________________________________________________________________________ 19 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers set r74h[4:3] to a value other than 00 to select autoretry mode (see table 14). in this configuration, the device stops monitoring after a critical fault event then moni - tors again following the boot-up delay plus 20ms (see the boot-up delay section). use r74h[2:0] to select an autoretry delay from 20ms to 1.6s. see table 14 for more information on setting the autoretry delay. when fault information is stored in flash (see the critical faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. when fault information is stored in flash and latch-on-fault mode is chosen, toggle en or reset the software enable bit only after the completion of the storing operation. when saving information about the failed lines only, ensure a delay of at least 102ms before the restart procedure. otherwise, ensure a mini - mum 153ms timeout, to ensure that adc conversions are completed and values are stored correctly in flash. reset output the reset output, reset, indicates the status of the monitored inputs. it asserts during the boot phase and deasserts following the reset timeout period once the monitored input voltage is within the undervoltage/over - voltage. during normal monitoring, reset can be configured to assert when any combination of mon_ inputs violates configurable combinations of undervoltage or overvolt - age thresholds. select the combination of mon_ inputs using r3ch[5:0] and r3dh[5:0]. note that mon_ inputs configured as critical faults always cause reset to assert regardless of these configuration bits. reset can be configured as push-pull or open drain using r3bh[3], and active high or active low using r3bh[2]. select the reset timeout by loading a value from table 15 into r3bh[7:4]. to generate a one-shot pulse on reset, write a 1 into r3bh[0]. the pulse width is the configured reset timeout. register bit r3bh[0] clears automatically (see table 15). the current state of reset can be checked by reading r20h[0]. table 14. autoretry configuration register address flash address bit range description 74h 274h [2:0] retry delay 000 = 20ms 001 = 40ms 010 = 80ms 011 = 150ms 100 = 280ms 101 = 540ms 110 = 1s 111 = 2s [4:3] autoretry/latch mode 00 = latch 01 = retry 1 time 10 = retry 3 times 11 = always retry
20 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers table 15. reset output configuration register address flash address bit range description 3bh 23bh [0] reset soft trigger 0 = normal reset behavior 1 = force reset to assert [1] not used [2] 0 = active low 1 = active high [3] 0 = open drain 1 = push-pull [7:4] reset timeout period 0000 = 25 f s 0001 = 1.5ms 0010 = 2.5ms 0011 = 4ms 0100 = 6ms 0101 = 10ms 0110 = 15ms 0111 = 25ms 1000 = 40ms 1001 = 60ms 1010 = 100ms 1011 = 150ms 1100 = 250ms 1101 = 400ms 1110 = 600ms 1111 = 1s 3ch 23ch [0] 1 = reset depends on mon1 undervoltage [1] 1 = reset depends on mon2 undervoltage [2] 1 = reset depends on mon3 undervoltage [3] 1 = reset depends on mon4 undervoltage [4] 1 = reset depends on mon5 undervoltage [5] 1 = reset depends on mon6 undervoltage [7:6] not used 3dh 23dh [0] 1 = reset depends on mon1 overvoltage [1] 1 = reset depends on mon2 overvoltage [2] 1 = reset depends on mon3 overvoltage [3] 1 = reset depends on mon4 overvoltage [4] 1 = reset depends on mon5 overvoltage [5] 1 = reset depends on mon6 overvoltage [7:6] not used
______________________________________________________________________________________ 21 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers watchdog timer the watchdog timer operates together with or indepen - dently of the MAX16068. when operating in dependent mode, the watchdog is not activated until reset is deasserted. when operating in independent mode, the watchdog timer activates immediately after v cc exceeds the uvlo threshold and the boot phase is complete. set r73h[4] to 0 to configure the watchdog in dependent mode. set r73h[4] to 1 to configure the watchdog in independent mode. see table 16 for more information on configuring the watchdog timer in depen - dent or independent mode. the watchdog timer can be reset by toggling the wdi inputs (gpio4) or by writing a 1 to r75h[5]. dependent watchdog timer operation use the watchdog timer to monitor f p activity in two modes. flexible timeout architecture provides an adjust - able watchdog startup delay of up to 300s, allowing complicated systems to complete lengthy boot-up rou - tines. an adjustable watchdog timeout allows the super - visor to provide quick alerts when the processor activity fails. after each reset event (v cc drops below uvlo then returns above uvlo, software reboot, manual reset (mr), en input going low then high, or watchdog reset), the watchdog startup delay provides an extended time for the system to power up and fully initialize all f p and system components before assuming responsibility for routine watchdog updates. set r76h[6:4] to a value other than 000 to enable the watchdog startup delay. set r76h[6:4] to 000 to disable the watchdog startup delay. the normal watchdog timeout period, t wdi , begins after the first transition on wdi before the conclusion of the long startup watchdog period, t wdi_startup (figures 3 and 4). during the normal operating mode, wdo asserts if the f p does not toggle wdi with a valid transition (high- to-low or low-to-high) within the standard timeout period, t wdi . wdo remains asserted until wdi is toggled or reset is asserted (figure 4). while en is low, the watchdog timer is in reset. the watchdog timer does not begin counting until the moni - toring starts and reset is deasserted. the watchdog timer is reset and wdo deasserts any time reset is asserted (figure 5). the watchdog timer is held in reset while reset is asserted. figure 3. normal watchdog startup sequence figure 4. watchdog timer operation last mon_ wdi v th t wdi_startup < t wdi t rp reset < t wdi wdi wdo 0v v cc 0v v cc < t wdi < t wdi < t wdi < t wdi > t wdi < t wdi < t wdi t wdi
22 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers figure 5. watchdog startup sequence with watchdog reset enable bit set to 1 table 16. watchdog configuration wdi wdo 0v 0v v cc v cc 0v v cc < t wdi 1s reset < t wdi t wdi t rp < t wdi_startup register address flash address bit range description 73h 273h [4] 1 = independent mode 0 = dependent mode 76h 276h [7] 1 = watchdog reset output enabled 0 = watchdog reset output disabled [6:4] watchdog startup delay 000 = no initial timeout 001 = 30s 010 = 40s 011 = 80s 100 = 120s 101 = 160s 110 = 220s 111 = 300s [3:0] watchdog timeout 0000 = watchdog disabled 0001 = 1ms 0010 = 2ms 0011 = 4ms 0100 = 8ms 0101 = 14ms 0110 = 27ms 0111 = 50ms 1000 = 100ms 1001 = 200ms 1010 = 400ms 1011 = 750ms 1100 = 1.4s 1101 = 2.7s 1110 = 5s 1111 = 10s
______________________________________________________________________________________ 23 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers the watchdog can be configured to control the reset output as well as the wdo output. reset asserts for the reset timeout, t rp , when the watchdog timer expires and the watchdog reset output enable bit (r76h[7]) is set to 1. when reset is asserted, the watchdog timer is cleared and wdo is deasserted, therefore, wdo pulses low for a short time (approximately 1 f s) when the watchdog timer expires. reset is not affected by the watchdog timer when the watchdog reset output enable bit (r76h[7]) is set to 0. if a reset is asserted by the watchdog timeout, the wdreset bit is set to 1. a connected processor can check this bit to see the reset was due to a watchdog timeout. see table 16 for more information on configuring watch - dog functionality. independent watchdog timer operation when r73h[3] is 1, the watchdog timer operates in the independent mode. in the independent mode, the watchdog timer operates as if it were a separate device. the watchdog timer is activated immediately upon v cc exceeding uvlo and once the boot-up sequence is finished. when reset is asserted by en being low, the watchdog timer and wdo are not affected. there is a startup delay if r76h[6:4] is set to a value dif - ferent than 000. if r76h[6:4] is set to 000, there is not a startup delay. see table 16 for delay times. in independent mode, if the watchdog reset output enable bit r76h[7] is set to 1, when the watchdog timer expires, wdo asserts then reset asserts. wdo then deasserts. wdo is low for approximately 1 f s. if the watchdog reset output enable bit (r76h[7]) is set to 0, when the watchdog timer expires, wdo asserts but reset is not affected. user-defined register register r8ah provides storage space for a user-defined configuration or firmware version number. note that this register controls the contents of the jtag usercode register bits 7-0. the user-defined register is stored at r28ah in the flash memory. memory lock bits register r8ch contains the lock bits for the configuration registers, configuration flash, user flash, and fault regis - ter lock. see table 17 for details. smbus-compatible interface the MAX16068 features an smbus-compatible, 2-wire serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facilitate bidirectional communication between the MAX16068 and the master device at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the MAX16068 is a transmit/receive, slave-only device, rely - ing upon a master device to generate a clock signal. the master device (typically a microcontroller) initiates a data transfer on the bus and generates scl to permit that transfer. table 17. memory lock bits register address flash address bit range description 8ch 28ch [0] configuration register lock 1 = locked 0 = unlocked [1] flash fault register lock 1 = locked 0 = unlocked [2] flash configuration lock 1 = locked 0 = unlocked [3] user flash lock 1 = locked 0 = unlocked [7.4] not used
24 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers a master device communicates to the MAX16068 by transmitting the proper address followed by command and/or data words. the slave address input, a0, is capable of detecting four different states, allowing mul - tiple identical devices to share the same serial bus. the slave address is described further in the slave address section. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is an open-drain input/ output. scl and sda both require external pullup resis - tors to generate the logic-high voltage. use 4.7k i for most applications. bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high (figure 6); otherwise, the MAX16068 registers a start or stop condition (figure 7) from the master. sda and scl idle high when the bus is not busy. start and stop conditions both scl and sda idle high when the bus is not busy. a master device signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. the master device issues a stop condition by transitioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is generated, such as in the block read protocol (see figure 1, smbus timing diagram). early stop conditions the MAX16068 recognizes a stop condition at any point during transmission except if a stop condition occurs in the same high pulse as a start condition. this condition is not a legal smbus format; at least one clock pulse must separate any start and stop condition. repeated start conditions a repeated start can be sent instead of a stop condition to maintain control of the bus during a read operation. the start and repeated start conditions are functionally identical. figure 6. bit transfer figure 7. start and stop conditions data line stable, data valid sda scl change of data allowed p s start condition sda scl stop condition
______________________________________________________________________________________ 25 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always gener - ates an ack. the MAX16068 generates an ack when receiving an address or data by pulling sda low during the 9th clock period (figure 8). when transmitting data, such as when the master device reads data back from the MAX16068, the device waits for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if the receiving device is busy or if a sys - tem fault has occurred. in the event of an unsuccessful data transfer, the bus master can reattempt communica - tion at a later time. the MAX16068 generates a nack after the command byte received during a software reboot, while writing to the flash, or when receiving an illegal memory address. slave address use the slave address input, a0, to allow multiple identi - cal devices to share the same serial bus. connect a0 to gnd, dbp (or an external supply voltage greater than 2v), scl, or sda to set the device address on the bus. see table 18 for a listing of all possible 7-bit addresses. the slave address can also be set to a custom value by loading the address into register r8bh[6:0]. see table 19. if r8bh[6:0] is loaded with 00h, the address is set by input a0. do not set the address to 09h or 7fh to avoid address conflicts. the slave address setting takes effect immediately after writing to the register. figure 8. acknowledge table 18. setting the smbus slave address r = read/write select bit. scl 1 s 2 8 9 sda by transmitter sda by receiver clock pulse for acknowledge nack ack slave addresses a0 slave address 0 1010 100r 1 1010 101r scl 1010 110r sda 1010 111r
26 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers packet error checking (pec) the MAX16068 features a packet-error checking (pec) mode that is useful to improve the reliability of the com - munication bus by detecting bit errors. by enabling pec, an extra crc-8 error check byte is added in the data string during each read and/or write sequence. enable pec by writing a 1 to r8bh[7]. the crc-8 byte is calculated using the polynomial: c = x 8 + x 2 + x + 1 the pec calculation includes all bytes in the transmis - sion, including address, command and data. the pec calculation does not include ack, nack, start, stop, or repeated start. command codes the MAX16068 uses eight command codes for block read, block write, and other commands. see table 20 for a list of command codes. to initiate a software reboot, send a7h using the send byte format. a software-initiated reboot is function - ally the same as a hardware-initiated power-on reset. during boot-up, flash configuration data in the range of 230hC28ch is copied to r30hCr8ch registers in the default page. send command code a8h to trigger a fault store to flash. configure the critical fault log control register (6dh) to store adc conversion results and/or fault flags. while in the flash page, send command code a9h to access the flash page (addresses from 200hC2ffh). once command code a9h has been sent, all addresses are recognized as flash addresses only. send command code aah to return to the default page (addresses from 000hC0ffh). send command code abh to access the user flash-page (addresses from 300hC3ffh), and send command code ach to return to the flash page. restrictions when writing to flash flash must be written to 8 bytes at a time. the initial address must be aligned to 8-byte boundariesthe 3 lsbs of the initial address must be 000. write the 8 bytes using a single block write command or using eight successive write byte commands. a write operation requires 122ms for each 8-byte block. after program - ming a block, check r20h[1] (see table 25) to make sure the write operation is complete before attempting to write the next block. table 20. command codes table 19. smbus settings register command code action a5h block write a6h block read a7h reboot flash in register file a8h trigger emergency save to flash a9h flash page access on aah flash page access off abh user flash access on (must be in flash page already) ach user flash access off (return to flash page) register address flash address bit range description 8bh 28bh [6:0] smbus slave address register. set to 00h to use a0 pin address setting. [7] 1 = enable pec (packet error check).
______________________________________________________________________________________ 27 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 9). the send byte presets a register pointer address for a subsequent read or write. the slave sends a nack instead of an ack if the master tries to send a memory address or command code that is not allowed. if the master sends a5h or a6h, the data is ack, because this could be the start of the write block or read block. if the master sends a stop condition before the slave asserts an ack, the internal address pointer does not change. if the master sends a7h, this signifies a software reboot. the send byte procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address or com - mand code. 5) the addressed slave asserts an ack (or nack) on sda. 6) the master sends a stop condition. receive byte the receive byte protocol allows the master device to read the register content of the MAX16068 (see figure 9). the flash or register address must be preset with a send byte or write word protocol first. once the read is complete, the internal pointer increases by one. repeating the receive byte protocol reads the contents of the next address. the receive byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a read bit (high). 3) the addressed slave asserts an ack on sda. 4) the slave sends 8 data bits. 5) the master asserts a nack on sda. 6) the master generates a stop condition. write byte the write byte protocol (see figure 9) allows the mas - ter device to write a single byte in the default page, extended page, or flash page, depending on which page is currently selected. the write byte procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. 8) the master sends a stop condition. to write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. the data byte is written to the addressed location if the memory address is valid. the slave asserts a nack at step 5 if the mem - ory address is not valid. when pec is enabled, the write byte protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends an 8-bit command code. 5) the active slave asserts an ack on the data line. 6) the master sends an 8-bit data byte. 7) the slave asserts an ack on the data line. 8) the master sends an 8-bit pec byte. 9) the slave asserts an ack on the data line (if pec is good, otherwise nack). 10) the master generates a stop condition. read byte the read byte protocol (see figure 9) allows the master device to read a single byte located in the default page, extended page, or flash page depending on which page is currently selected. the read byte procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the addressed slave asserts an ack on sda.
28 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers 9) the slave sends an 8-bit data byte. 10) the master asserts a nack on sda. 11) the master sends a stop condition. if the memory address is not valid, it is nacked by the slave at step 5 and the address pointer is not modified. when pec is enabled, the read byte protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8 data bits. 5) the active slave asserts an ack on the data line. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave id plus a read bit (high). 8) the addressed slave asserts an ack on the data line. 9) the slave sends 8 data bits. 10) the master asserts an ack on the data line. 11) the slave sends an 8-bit pec byte. 12) the master asserts a nack on the data line. 13) the master generates a stop condition. block write the block write protocol (see figure 9) allows the master device to write a block of data (1C16 bytes) to memory. preload the destination address by a previous send byte command; otherwise the block write command begins to write at the current address pointer. after the last byte is written, the address pointer remains preset to the next valid address. if the number of bytes to be written causes the address pointer to exceed 8fh for configura - tion registers or configuration flash or ffh for user flash, the address pointer stays at 8fh or ffh, respectively, overwriting this memory address with the remaining bytes of data. the slave generates a nack at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered. the block write procedure is as follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for block write (94h). 5) the addressed slave asserts an ack on sda. 6) the master sends the 8-bit byte count (1 byte to 16 bytes), n. 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 n - 1 times. 11) the master sends a stop condition. when pec is enabled, the block write protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4) the master sends 8 bits of the block write command code. 5) the slave asserts an ack on the data line. 6) the master sends 8 bits byte count (min 1, max 16) n. 7) the slave asserts an ack on the data line. 8) the master sends 8 bits of data. 9) the slave asserts an ack on the data line. 10) repeat 8 and 9 n - 1 times. 11) the master sends an 8-bit pec byte. 12) the slave asserts an ack on the data line (if pec is good, otherwise nack). 13) the master generates a stop condition. block read the block read protocol (see figure 9) allows the master device to read a block of up to 16 bytes from memory. read fewer than 16 bytes of data by issuing an early stop condition from the master, or by generating a nack with the master. the destination address should be preloaded by a previous send byte command; otherwise, the block read command begins to read at the current address pointer. if the number of bytes to be read causes the address pointer to exceed 8fh for the configuration register or configuration flash or ffh in user flash, the address pointer stays at 8fh or ffh, respectively.
______________________________________________________________________________________ 29 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers figure 9. smbus protocols send byte format s address slave address: address of the slave on the serial interface bus. data byte: presets the internal address pointer or represents a command. r/w ack command ack p 7 bits 0 0 0 8 bits receive byte format s address slave address: address of the slave on the serial interface bus. data byte: data is read from the location pointed to by the internal address pointer. r/w ack data nack p 7 bits 1 0 0 1 1 8 bits write byte format s address slave address: address of the slave on the serial interface bus. command byte: sets the internal address pointer. r/w ack command ack 7 bits 0 0 0 0 8 bits data byte: data is written to the locations set by the internal address pointer. data ack p 8 bits read byte format s slave address slave address: address of the slave on the serial interface bus. command byte: sets the internal address pointer. r/w r/w ack command ack 7 bits 0 0 0 0 1 8 bits data byte: data is written to the locations set by the internal address pointer. sr r/w r/w slave address r/w 7 bits 1 block write format s address slave address: address of the slave on the serial interface bus. command byte: fah data byte: data is written to the locations set by the internal address pointer. ack command ack 7 bits 0 0 0 0 0 0 0 8 bits byte count = n ack p 8 bits data byte 1 ack 8 bits data byte n ack 8 bits data byte ? ack ack data byte 8 bits 8 bits smbalert# alert response address: only the device that interrupted the master responds to this address. slave address: slave places its own address on the serial bus. s address r/w ack data nack p 0001100 d.c. 8 bits nack p slave to master master to slave block read format s address slave address: address of the slave on the serial interface bus. s = start condition p = stop condition sr = repeated start condition d.c. = don?t care ack = acknowledge, sda pulled low during rising edge of scl. nack = not acknowledge, sda left high during rising edge of scl. all data is clocked in/out of the device on rising edges of scl. = sda transitions from high to low during period of scl. = sda transitions from low to high during period of scl. command byte: fbh data byte: data is read from the locations set by the internal address pointer. ack command ack 7 bits address slave address: address of the slave on the serial interface bus. 7 bits 0 0 0 0 0 0 0 1 8 bits ack p 8 bits data byte n ack 8 bits ack data byte n 8 bits data byte ? nack 8 bits sr ack 1 byte count = n s address command pec p 7 bits 0 0 8 bits 0 write byte format with pec read byte format with pec block write with pec block read with pec data 0 8 bits 0 8 bits s s s address command data pec p p sr sr address 0 0 0 1 0 0 0 0 0 0 0 0 nack 1 p 0 0 0 8 bits 0 0 0 8 bits command 8 bits command 8 bits 0 0 0 8 bits data n 8 bits data n 8 bits pec 8 bits pec 8 bits 0 7 bits address 7 bits address 7 bits 1 1 7 bits byte count n 8 bits byte count n 8 bits address 7 bits data byte 1 8 bits data byte 1 8 bits data byte 8 bits data byte 8 bits r/w r/w r/w r/w r/w r/w ack ack ack ack ack ack ack ack nack ack ack ack ack ack ack ack ack ack ack ack ack ack ack
30 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers the block read procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read command (95h). 5) the slave asserts an ack on sda, unless busy. 6) the master generates a repeated start condi - tion. 7) the master sends the 7-bit slave address and a read bit (high). 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 11 and 12 up to fifteen times. 14) the master asserts a nack on sda. 15) the master sends a stop condition. figure 10. jtag block diagram test access port (tap) controller instruction register [length = 5 bits] bypass register [length = 1 bit] identification register [length = 32 bits] user code register [length = 32 bits] memory address register [length = 8 bits] memory read register [length = 8 bits] memory write register [length = 8 bits] 11111 00000 00011 00100 00101 00110 00111 mux 2 tdo tdi tms tck 01000 registers and eeprom 01001 01010 01011 01100 mux 1 00111 01000 01001 01010 01011 01100 reboot save setusrflsh rstflshadd rstusrflsh setflshadd command decoder r pu v db
______________________________________________________________________________________ 31 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers when pec is enabled, the block read protocol becomes: 1) the master sends a start condition. 2) the master sends the 7-bit slave id plus a write bit (low). 3) the addressed slave asserts an ack on the data line. 4 the master sends 8 bits of the block read command code. 5) the slave asserts an ack on the data line unless busy. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave id plus a read bit (high). 8) the slave asserts an ack on the data line. 9) the slave sends 8-bit byte count (16). 10) the master asserts an ack on the data line. 11) the slave sends 8 bits of data. 12) the master asserts an ack on the data line. 13) repeat 11 and 12 up to 15 times. 14) the slave sends an 8-bit pec byte. 15) the master asserts a nack on the data line. 16) the master generates a stop condition. smbalert ( alert ) the MAX16068 supports the smbus alert protocol. to enable the smbus alert output, set r40h[4] to 1, then configure gpio1 to act as the smbus alert ( alert ) according to table 12. this output is open drain and uses the wired-or configuration with other devices on the smbus. during a fault, the MAX16068 asserts alert low, signaling the master that an interrupt has occurred. the master responds by sending the ara (alert response address) protocol on the smbus. this protocol is a read byte with 09h as the slave address. the slave acknowledges the ara (09h) address and sends its own smbus address to the master. the slave then deasserts alert . the master can then query the slave and determine the cause of the fault. by checking r1c[7], the master can confirm that the MAX16068 trig - gered the smbus alert. the master must send the ara before clearing r1ch[7]. clear r1ch[7] by writing a 1. if gpio1 is configured as the smbus alert output but the smbus alert feature is disabled (r40h[4] is set to 0), gpio1 acts as an additional fault output. jtag serial interface the MAX16068 features a jtag port that complies with a subset of the ieee 1149.1 specification. either the smbus or the jtag interface can be used to access internal memory; however, only one interface is allowed to run at a time. the MAX16068 contains extra jtag instructions and registers not included in the jtag specification that provide access to internal memory. the extra instructions include load address, write, read, reboot, and save. test access port (tap) controller state machine the tap controller is a finite state machine that responds to the logic level at tms on the rising edge of tck. see figure 11 for a diagram of the finite state machine. the possible states are described as follows: test-logic-reset: at power-up, the tap controller is in the test-logic-reset state. the instruction register contains the idcode instruction. all system logic of the device operates normally. this state can be reached from any state by driving tms high for five clock cycles. run-test/idle: the run-test/idle state is used between scan operations or during specific tests. the instruction register and test data registers remain idle. select-dr-scan: all test data registers retain their previ - ous state. with tms low, a rising edge of tck moves the controller into the capture-dr state and initiates a scan sequence. tms high during a rising edge on tck moves the controller to the select-ir-scan state. capture-dr: data can be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. on the rising edge of tck, the controller goes to the shift-dr state if tms is low or it goes to the exit1-dr state if tms is high. shift-dr: the test data register selected by the current instruction connects between tdi and tdo and shifts data one stage toward its serial output on each rising edge of tck while tms is low. on the rising edge of tck, the controller goes to the exit1-dr state if tms is high. exit1-dr: while in this state, a rising edge on tck puts the controller in the update-dr state. a rising edge on tck with tms low puts the controller in the pause-dr state.
32 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers pause-dr: shifting of the test data registers halts while in this state. all test data registers retain their previous state. the controller remains in this state while tms is low. a rising edge on tck with tms high puts the con - troller in the exit2-dr state. exit2-dr: a rising edge on tck with tms high while in this state puts the controller in the update-dr state. a ris - ing edge on tck with tms low enters the shift-dr state. update-dr: a falling edge on tck while in the update- dr state latches the data from the shift register path of the test data registers into a set of output latches. this prevents changes at the parallel output because of changes in the shift register. on the rising edge of tck, the controller goes to the run-test/idle state if tms is low or goes to the select-dr-scan state if tms is high. select-ir-scan: all test data registers retain the previ - ous states. the instruction register remains unchanged during this state. with tms low, a rising edge on tck moves the controller into the capture-ir state. tms high during a rising edge on tck puts the controller back into the test-logic-reset state. capture-ir: use the capture-ir state to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of tck. if tms is high on the rising edge of tck, the controller enters the exit1-ir state. if tms is low on the rising edge of tck, the controller enters the shift-ir state. shift-ir: in this state, the shift register in the instruction register connects between tdi and tdo and shifts data one stage for every rising edge of tck toward the tdo serial output while tms is low. the parallel outputs of the instruction register as well as all test data registers remain at the previous states. a rising edge on tck with tms high moves the controller to the exit1-ir state. a rising edge on tck with tms low keeps the controller in the shift-ir state while moving data one stage through the instruction shift register. figure 11. tap controller state diagram test-logic-reset 1 1 1 1 0 0 run-test/idle 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1 select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 0 0 0 0 1 1 0 1 1
______________________________________________________________________________________ 33 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers exit1-ir: a rising edge on tck with tms low puts the controller in the pause-ir state. if tms is high on the ris - ing edge of tck, the controller enters the update-ir state. pause-ir: shifting of the instruction shift register halts temporarily. with tms high, a rising edge on tck puts the controller in the exit2-ir state. the controller remains in the pause-ir state if tms is low during a rising edge on tck. exit2-ir: a rising edge on tck with tms high puts the controller in the update-ir state. the controller loops back to shift-ir if tms is low during a rising edge of tck in this state. update-ir: the instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of tck as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on tck with tms low puts the controller in the run- test/idle state. with tms high, the controller enters the select-dr-scan state. instruction register the instruction register contains a shift register as well as a latched 5-bit wide parallel output. when the tap controller enters the shift-ir state, the instruction shift register connects between tdi and tdo. while in the shift-ir state, a rising edge on tck with tms low shifts the data one stage toward the serial output at tdo. a rising edge on tck in the exit1-ir state or the exit2-ir state with tms high moves the controller to the update- ir state. the falling edge of that same tck latches the data in the instruction shift register to the instruction register parallel output. table 21 shows the instructions supported by the MAX16068 and the respective opera - tional binary codes. bypass: when the bypass instruction is latched into the instruction register, tdi connects to tdo through the 1-bit bypass test data register. this allows data to pass from tdi to tdo without affecting the devices operation. idcode: when the idcode instruction is latched into the parallel instruction register, the identification data register is selected. the device identification code is loaded into the identification data register on the rising edge of tck following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially through tdo. during test-logic-reset, the idcode instruction is forced into the instruction register. the identification code always has a 1 in the lsb posi - tion. the next 11 bits identify the manufacturers jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. see table 22. table 21. jtag instruction set table 22. 32-bit identification code instruction code notes bypass 0x1f mandatory instruction code idcode 0x00 load manufacturer id code/part number usercode 0x03 load user code load address 0x04 load address register content read data 0x05 read data pointed by current address write data 0x06 write data pointed by current address reboot 0x07 reboot flash data content into register file save 0x08 trigger emergency save to flash setflshadd 0x09 flash page access on rstflshadd 0x0a flash page access off setusrflsh 0x0b user flash access on (must be in flash page already) rstusrflsh 0x0c user flash access off (return to flash page) msb lsb version (4 bits) part number (16 bits) manufacturer (11 bits) fixed value (1 bit) 0001 1000000000000010 00011001011 1
34 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers usercode: when the usercode instruction latches into the parallel instruction register, the user-code data register is selected. the device user-code loads into the user-code data register on the rising edge of tck fol - lowing entry into the capture-dr state. shift-dr can be used to shift the user-code out serially through tdo. see table 24. this instruction can be used to help identify multiple MAX16068 devices connected in a jtag chain. load address: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the MAX16068. when the load address instruction latches into the instruction register, tdi con - nects to tdo through the 8-bit memory address test data register during the shift-dr state. read data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the MAX16068. when the read instruction latches into the instruction register, tdi connects to tdo through the 8-bit memory read test data register during the shift-dr state. write data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the MAX16068. when the write instruction latches into the instruction register, tdi connects to tdo through the 8-bit memory write test data register during the shift-dr state. reboot: this is an extension to the standard ieee 1149.1 instruction set to initiate a software-controlled reset to the MAX16068. when the reboot instruc - tion latches into the instruction register, the MAX16068 resets and immediately begins the boot-up sequence. save: this is an extension to the standard ieee 1149.1 instruction set that triggers a fault log. the current adc conversion results along with fault information are saved to flash depending on the configuration of the critical fault log control register (r6dh). setflshadd: this is an extension to the standard ieee 1149.1 instruction set that allows access to the flash page. flash registers include adc conversion results, dacout enables, and gpio input/output data. use this page to access registers 200hC2ffh. rstflshadd: this is an extension to the standard ieee 1149.1 instruction set. use rstflshadd to return to the default page and disable access to the flash page. setusrflsh: this is an extension to the standard ieee 1149.1 instruction set that allows access to the user flash page. when on the configuration flash page, send the setusrflsh command, all addresses are recog - nized as flash addresses only. use this page to access registers 300hC3ffh. rstusrflsh: this is an extension to the standard ieee 1149.1 instruction set. use rstusrflsh to return to the configuration flash page and disable access to the user flash. restrictions when writing to flash flash must be written to 8 bytes at a time. the initial address must be aligned to 8-byte boundariesthe 3 lsbs of the initial address must be 000. write the 8 bytes using eight successive write data commands. a write operation requires 122ms for each 8-byte block. after programming a block, check r20h[1] (see table 25) to make sure the write operation is complete before attempting to write the next block. table 23. 32-bit user-code data table 24. maximum write time msb lsb dont care smbus slave id user id ( r 8a[7:0]) 00000000000000000 see table 18 r6dh[1:0] value description maximum write time (ms) 00 save flags and adc readings 153 01 save flags 102 10 save adc readings 153 11 do not save anything
______________________________________________________________________________________ 35 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers applications information device behavior at power-up when v cc is ramped from 0v, the reset output is high impedance until v cc reaches 1.4v, at which point reset goes low. all other outputs are high impedance until v cc reaches 2.7v, then the flash contents are cop - ied into register memory. this takes 150 f s (max) after which the outputs assume their programmed states. programming the MAX16068 in circuit the MAX16068 can be programmed in the application circuit by taking into account the following points during circuit design: u the MAX16068 needs to be powered from an inter - mediate voltage bus or an auxiliary voltage supply so programming can occur even when the boards power supplies are off. this could also be achieved by using oring diodes so that power can be provided through the programming connector. u the smbus or jtag bus lines should not connect through a bus multiplexer powered from a voltage rail controlled by the MAX16068. if the device needs to be controlled by an on-board f p, consider connecting the f p to one bus (such as smbus) and use the other bus for in-circuit programming. maintaining power during a fault condition power to the MAX16068 must be maintained for a spe - cific period of time to ensure a successful flash fault log operation during a fault that removes power to the circuit. table 25 shows that the amount of time required depends on the settings in the fault control register (r6dh[1:0]). maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capacitor between the voltage source, v in , and v cc (figure 12). the capacitor value depends on v in and the time delay required, t fault_save . use the following formula to cal - culate the capacitor size: c = (t fault_save x i cc(max) )/(v in - v diode - v uvlo ) where the capacitance is in farads and t fault_save is in seconds, i cc(max) is 14ma, v diode is the voltage drop across the diode, and v uvlo is 2.7v. for example, with a v in of 14v, a diode drop of 0.7v, and a t fault_save of 153ns, the minimum required capacitance is 202 f f. table 25. reset state, flash state, and reset reason figure 12. power circuit for shutdown during fault conditions register address bit range description r20h [0] reset output state 0 = reset is low 1 = reset is high [1] 1 = flash memory is busy [2] 1 = last reset asserted due to en going low [3] 1 = last reset asserted due to watchdog timeout [7:4] not used MAX16068 v cc c v in gnd
36 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers configuring the device an evaluation kit and a graphical user interface (gui) are available to create a custom configuration for the device (figure 13). refer to the MAX16068 evaluation kit for configuration. cascading multiple MAX16068s multiple MAX16068s can be cascaded to monitor more power supplies. there are many ways to cascade the devices depending on the desired behavior. in general, there are several techniques as follows: u configure a gpio on each device to be extfault (open drain). externally wire them together with a sin - gle pullup resistor. set register bits r72h[5] and r6dh[2] to 1 so that all faults propagate between devices. if a critical fault occurs on one device, extfault asserts, triggering the nonvolatile fault logger in all cascaded devices and recording a snapshot of all system volt - ages. u connect open-drain reset outputs together to obtain a master system reset signal. u connect all en inputs together for a master enable signal. layout and bypassing bypass dbp and abp each with a 1 f f ceramic capacitor to gnd. bypass v cc with a 10 f f capacitor to ground. avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or abps bypass capacitor ground connection. use dedicated analog and digital ground planes. connect the capacitors as close as possible to the device. figure 13. graphical user interface screenshot
______________________________________________________________________________________ 37 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers register map flash address register address read/ write description adc values, fault registers, gpio_s as input portsnot in flash 000 r mon1 adc output, msbs 001 r mon1 adc output, lsbs 002 r mon2 adc output, msbs 003 r mon2 adc output, lsbs 004 r mon3 adc output, msbs 005 r mon3 adc output, lsbs 006 r mon4 adc output, msbs 007 r mon4 adc output, lsbs 008 r mon5 adc output, msbs 009 r mon5 adc output, lsbs 00a r mon6 adc output, msbs 00b r mon6 adc output, lsbs 00cC01a reserved 01b r/w fault registerfailed line flags 01c r/w fault registerfailed line flags 01d reserved 01e r gpio_ data in (read only) 01f reserved 020 r/w flash status/reset output monitor 021 reserved gpio_ and output dependencies/configurations 230 030 reserved 231 031 reserved 232 032 reserved 233 033 reserved 234 034 reserved 235 035 reserved 236 036 r/w fault dependencies 237 037 r/w fault dependencies 238C23a 038C03a reserved 23b 03b r/w reset output configuration 23c 03c r/w reset output dependencies 23d 03d r/w reset output dependencies 23e 03e r/w gpio data out 23f 03f r/w gpio configuration 240 040 r/w gpio configuration, aranen (ara enable) 241C242 041C042 reserved
38 _____________________________________________________________________________________ MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers register map (continued) flash address register address read/ write description adcconversions 243 043 r/w adcs voltage ranges for mon_ monitoring 244 044 r/w adcs voltage ranges for mon_ monitoring 245C247 045C047 reserved input thresholds 248 048 reserved 249 049 r/w mon1 ov threshold 24a 04a r/w mon1 uv threshold 24b 04b reserved 24c 04c r/w mon2 ov threshold 24d 04d r/w mon2 uv threshold 24e 04e reserved 24f 04f r/w mon3 ov threshold 250 050 r/w mon3 uv threshold 251 051 reserved 252 052 r/w mon4 ov threshold 253 053 r/w mon4 uv threshold 254 054 reserved 255 055 r/w mon5 ov threshold 256 056 r/w mon5 uv threshold 257 057 reserved 258 058 r/w mon6 ov threshold 259 059 r/w mon6 uv threshold 25aC26c 05aC06c reserved fault setup 26d 06d r/w save after extfault fault control 26e 06e r/w faults causing store in flash 26f 06f r/w faults causing store in flash 270 070 r/w faults causing store in flash 271 071 reserved 272 072 r/w extfault enable
______________________________________________________________________________________ 39 MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers register map (continued) flash address register address read/ write description timeouts 273 073 r/w watchdog independent mode, margin enabled, soft reset functionality 274 074 r/w adc fault deglitch/autoretry configuration 275 075 r/w wdi toggle/fault timeout, reverse sequencing bit 276 076 r/w wdreset, wd timers 277 077 r/w boot-up delay 278 078 reserved 279 079 reserved 27a 07a reserved 27b 07b reserved 27c 07c reserved 27d 07d reserved miscellaneous 27e 07e reserved 27f 07f reserved 280 080 reserved 281C283 081C083 reserved 284 084 reserved 285 085 reserved 286 086 reserved 287C289 087C089 reserved 28a 08a r/w customer use (version) 28b 08b r/w pec enable/smbus address 28c 08c r/w lock bits 28d 08d r revision code
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 40 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX16068 6-channel, flash-configurable system manager with nonvolatile fault registers typical operating circuit chip information process: bicmos package information for the latest package outline information and land pat - terns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suf - fix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 28 tqfn-ep t2855+6 21-0140 en in +48v in out dc-dc mon3? mon6 3.3v mon1 mon2 v cc en reset scl sda fault out in dc-dc latch circuit out in dc-dc out in dc-dc dbp abp ao gnd MAX16068

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